Contemporary integrated circuit devices are typically constructed en masse on a semiconductor wafer of silicon or gallium arsenide. Each device generally takes the form of an integrated circuit (IC) die. If the die is to be encapsulated in a plastic package, it is first bonded to the die-mounting paddle of a leadframe which is attached to other leadframes in a leadframe strip. The wire attachment pads on the die are connected with their corresponding leads on the leadframe with aluminum or gold wire during a wire bonding process, following which the die is coated with a protective polyimide film. Finally, the die is encapsulated in plastic and the plastic-encapsulated chip undergoes a trim and form operation which separates the interconnected packages on the leadframe strip into individual entities and bends (forms) the leads of each package. The package is then recognizable as an IC "chip". The operation for manufacturing plastic-encapsulated packages is highly automated, allowing high quality and low cost.
IC packages take many forms, although the trend is clearly toward designs which increase mounting density. For years, the standard IC package was the dual-inline package or DIP. Such packages were typically through-hole soldered on printed circuit boards. A newer dual-inline lead design, known as small-outline J-lead package, has been rapidly supplanting the standard DIP design for two reasons. Firstly, the leads of an SOJ package are soldered to only one side of a circuit board, thus leaving the other side of the board free for the mounting of additional SOJ packages. Secondly, the leads are much less vulnerable to damage prior to board assembly, hence, there are fewer rejects. Both DIP and SOJ packages are horizontal packages (i.e., the die is mounted in a plane parallel to the board-attachment plane). A vertical package known as the zigzag inline package or ZIP is also coming into greater use. ZIPs are designed for through-hole-soldered connections on a circuit board. Since such packages require very little board area for connection, they are particularly useful where high-density applications are a must. Patents for self-supporting, surface-mount vertical packages have also been issued to Daniel A. Baudouin, et al (U.S. Pat. No. 4,975,763), and to Warren M. Farnworth (U.S. Pat. No. 4,967,262).
Package density may be increased by an order of magnitude by constructing multi-chip packages. Irvine Sensors Corporation (ISC) has been especially active in this field. Several noteworthy multi-chip modules, that have been developed by ISC employees, will be described below.
U.S. Pat. No. 4,983,533, issued to Tiong C. Go, discloses an electronic module comprised of multiple integrated circuit chips stacked on top of the other. The leads for each chip are exposed on one of the four vertical perimetric edges thereof. The chips are adhesively bonded together, with the lead-containing perimetric edges forming an access plane on the module. The exposed leads of the access plane are interconnected via bonding bumps to electrical traces on a substrate layer that is bonded to the access plane of the module. Although it is difficult to conceive of a more dense packaging arrangement, this type of module, although producible in a cost-plus contractual environment, poses a number of daunting problems which raise production costs to levels which are unacceptable in a commercial environment. Firstly, it is costly to produce chips having leads exposed on their edges. Secondly, the access plane must be produced with great precision in order to provide planarity tolerances which result in reliable substrate-to-access plane bonding. Thirdly, it is extremely difficult to cost-effectively burn-in each die before it is incorporated in the module. And fourthly, because of attrition rates associated with each assembly operation, the probability of creating perfect modules from each group of chips is relatively low.
U.S. Pat. No. 4,764,846, also issued to Mr. Go, which are stacked one on top of the other and adhesively bonded to one another. Each sub-module has a cavity, inside which one or more IC chips are located. Each sub-module has a metalization to which input/output pads on the chips(s) is (are) bonded. This metalization pattern extends to at least one edge of the sub-module, where it is exposed for interconnection. Once the various sub-modules have been adhesively bonded together, these pattern-carrying edges form an access plane. The cavity may be formed either by securing a rectangular frame to a chip-carrying substrate, or by etching a cavity in a single piece of material. Like the module of above-referred-to Go patent, the metalization patterns of the various modules are interconnected, via bonding bumps, to electrical traces on a substrate layer that is bonded to the access plane of the module. This module, although it does not achieve density on par with the module created by simply bonding chips together, does provide for reduced production costs, as each sub-module can be thoroughly tested and burned-in before the entire package is assembled. However, it still suffers from assembly attrition related to the module interconnection process and the relatively high costs associated with the edge bonding technique.
What is needed is an improved multi-chip module which features a more reliable and less-costly interconnection technique, which still retains the attribute of individual chip testability prior to module assembly.